LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 517

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
PWMMR0I
PWMMR0R
PWMMR0S
PWMMR1I
PWMMR1R
PWMMR1S
PWMMR2I
PWMMR2R
PWMMR2S
PWMMR3I
PWMMR3R
PWMMR3S
PWMMR4I
PWMMR4R
24.6.4 PWM Match Control Register (PWM1MCR - 0x4001 8014)
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The PWM Match Control Registers are used to control what operations are performed
when one of the PWM Match Registers matches the PWM Timer Counter. The function of
each of the bits is shown in
the PWMTC.
This interrupt is disabled.
Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.
This feature is disabled.
Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR0 matches the PWMTC.
This feature is disabled
the PWMTC.
This interrupt is disabled.
Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.
Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in
Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in
This feature is disabled.
set to 0 if PWMMR1 matches the PWMTC.
This feature is disabled.
Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in
the PWMTC.
This interrupt is disabled.
Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.
This feature is disabled.
Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR2 matches the PWMTC.
This feature is disabled
Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in
the PWMTC.
This interrupt is disabled.
Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.
This feature is disabled
Stop on PWMMR3: The PWMTC and PWMPC will be stopped and PWMTCR[0] will
be set to 0 if PWMMR3 matches the PWMTC.
This feature is disabled
Interrupt on PWMMR4: An interrupt is generated when PWMMR4 matches the value
in the PWMTC.
This interrupt is disabled.
Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.
This feature is disabled.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
449.
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
UM10360
© NXP B.V. 2010. All rights reserved.
517 of 840
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0