LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 378

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 343. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description
Table 344. Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description
Table 345. Extended Frame Start Address register (EFF_sa - address 0x4003 C00C) bit description
UM10360
User manual
Bit
1:0
10:2
31:11 -
Bit
1:0
11:2
31:12 -
Bit
1:0
10:2
31:11 -
Symbol
-
SFF_sa
Symbol
-
SFF_GRP_sa
Symbol
-
EFF_sa
16.14.3 Standard Frame Individual Start Address register (SFF_sa -
16.14.4 Standard Frame Group Start Address register (SFF_GRP_sa -
16.14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C)
[1]
[1]
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the
table is empty, write the same value in this register and the SFF_GRP_sa register
described below. For compatibility with possible future devices, write zeroes in bits 31:11
and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size
of the table of Standard IDs which the Acceptance Filter will search and (if found)
automatically store received messages in Acceptance Filter RAM.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the
table is empty, write the same value in this register and the EFF_GRP_sa register
described below. The largest value that should be written to this register is 0x800, when
both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table
RAM is used. For compatibility with possible future devices, please write zeroes in bits
31:11 and 1:0 of this register.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
[1]
0x4003 C004)
[1]
0x4003 C008)
[1]
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If
the table is empty, write the same value in this register and the EFF_sa register
described below. The largest value that should be written to this register is 0x800,
when only the Standard Individual table is used, and the last word (address 0x7FC)
in AF Lookup Table RAM is used. For compatibility with possible future devices,
please write zeroes in bits 31:12 and 1:0 of this register.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
0
NA
Reset Value
NA
0
NA
Reset Value
NA
0
NA
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