LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 412

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

18.1 Basic configuration
18.2 Features
18.3 Description
UM10360
User manual
The two SSP interfaces, SSP0 and SSP1 are configured using the following registers:
Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is
included as a legacy peripheral. Only one of these peripherals can be used at the any one
time.
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC17xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.
1. Power: In the PCONP register
2. Clock: In PCLKSEL0 select PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see
3. Pins: Select the SSP pins through the PINSEL registers
4. Interrupts: Interrupts are enabled in the SSP0IMSC register for SSP0 and SSP1IMSC
5. Initialization: There are two control registers for each of the SSP ports to be
6. DMA: The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA
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UM10360
Chapter 18: LPC17xx SSP0/1
Rev. 2 — 19 August 2010
PCSSP1 to enable SSP1.
Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).
Section
through the PINMODE registers
register for SSP1
Interrupt Set Enable register, see
configured: SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1.
See
controller (see
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Master or slave operation.
8 frame FIFOs for both transmit and receive.
4 to 16 bit data frame.
DMA transfers supported by GPDMA.
Section 18.6.1
4.7.3. In master mode, the clock must be scaled down (see
All information provided in this document is subject to legal disclaimers.
Section
Table
Rev. 2 — 19 August 2010
and
18.6.10). For GPDMA system connections, see
375. Interrupts are enabled in the NVIC using the appropriate
Section
(Table
18.6.2.
(Section
Table
46), set bit PCSSP0 to enable SSP0 and bit
50.
8.4).
(Section
8.5) and pin modes
© NXP B.V. 2010. All rights reserved.
Section
User manual
Table
18.6.5).
412 of 840
543.