LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 211

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
10.19 CRC calculation
UM10360
User manual
The calculation is used for several purposes:
The C pseudocode function below calculates the CRC on a frame taking the frame
(without FCS) and the number of bytes in the frame as arguments. The function returns
the CRC as a 32-bit integer.
int crc_calc(char frame_no_fcs[], int frame_len) {
}
For FCS calculation, this function is passed a pointer to the first byte of the frame and the
length of the frame without the FCS.
•
•
•
Generation the FCS at the end of the Ethernet frame.
Generation of the hash table index for the hash table filtering.
Generation of the destination and source address hash CRCs.
int
int
char byte; // current byte
int
int q0, q1, q2, q3;
crc = 0xFFFFFFFF;
for (i = 0; i < frame_len; i++) {
}
return crc;
i;
j;
crc; // CRC result
byte = *frame_no_fcs++;
for (j = 0; j < 2; j++) {
}
All information provided in this document is subject to legal disclaimers.
if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) {
} else {
}
if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) {
} else {
}
if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) {
} else {
}
if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) {
} else {
}
crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
byte >>= 4;
// iterator
// another iterator
q3 = 0x04C11DB7;
q3 = 0x00000000;
q2 = 0x09823B6E;
q2 = 0x00000000;
q1 = 0x130476DC;
q1 = 0x00000000;
q0 = 0x2608EDB8;
q0 = 0x00000000;
Rev. 2 — 19 August 2010
// temporary variables
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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