LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 835

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
31.6.2.1
31.6.2.2
31.6.2.3
31.6.3
31.6.3.1
31.6.4
Chapter 32: LPC17xx Flash memory interface and programming
32.1
32.2
32.3
32.3.1
32.3.1.1
32.3.2
32.3.2.1
32.3.2.2
32.3.2.3
32.3.2.4
32.3.2.5
32.3.2.6
32.3.2.7
32.3.2.8
32.4
32.5
32.6
32.7
32.7.1
32.7.2
32.7.3
32.7.4
32.7.5
32.7.6
32.7.7
32.7.8
32.7.9
32.7.10
Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace
33.1
33.2
33.3
33.4
UM10360
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Boot process flowchart . . . . . . . . . . . . . . . . . 619
Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 620
Code Read Protection (CRP) . . . . . . . . . . . . 621
ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 623
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Pin Description . . . . . . . . . . . . . . . . . . . . . . . 641
Peripheral-to-memory or memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Peripheral-to-peripheral DMA flow . . . . . . . . 609
Memory-to-memory DMA flow . . . . . . . . . . . 610
Interrupt requests . . . . . . . . . . . . . . . . . . . . . 610
Hardware interrupt sequence flow . . . . . . . . 611
Address generation . . . . . . . . . . . . . . . . . . . 611
Memory map after any reset. . . . . . . . . . . . . 616
Criterion for Valid User Code . . . . . . . . . . . . 616
Communication protocol . . . . . . . . . . . . . . . . 617
ISP command format . . . . . . . . . . . . . . . . . . 617
ISP response format . . . . . . . . . . . . . . . . . . . 617
ISP data format. . . . . . . . . . . . . . . . . . . . . . . 617
ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 618
ISP command abort . . . . . . . . . . . . . . . . . . . 618
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 618
RAM used by ISP command handler . . . . . . 618
RAM used by IAP command handler . . . . . . 618
Unlock <Unlock code> . . . . . . . . . . . . . . . . . 623
Set Baud Rate <Baud Rate> <stop bit> . . . . 624
Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 624
Write to RAM <start address> <number of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Read Memory <address> <no. of bytes> . . . 625
Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 626
Copy RAM to Flash <flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 626
Go <address> <mode>. . . . . . . . . . . . . . . . . 627
Erase sector(s) <start sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 627
Blank check sector(s) <sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 628
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
31.6.4.1
31.6.5
31.6.5.1
31.6.5.1.1 Programming the DMA controller for
31.6.5.1.2 Example of scatter/gather DMA. . . . . . . . . . 612
32.7.11
32.7.12
32.7.13
32.7.14
32.7.15
32.8
32.8.1
32.8.2
32.8.3
32.8.4
32.8.5
32.8.6
32.8.7
32.8.8
32.8.9
32.8.10
32.9
32.10
32.10.1
32.10.1.1 Signature generation address and control
32.10.1.2 Signature generation result registers . . . . . . 638
32.10.1.3 Flash Module Status register (FMSTAT -
32.10.1.4 Flash Module Status Clear register (FMSTATCLR
32.10.2
33.5
33.6
33.6.1
IAP commands . . . . . . . . . . . . . . . . . . . . . . . 631
JTAG flash programming interface . . . . . . . 636
Flash signature generation . . . . . . . . . . . . . 637
Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 642
Debug memory re-mapping . . . . . . . . . . . . . 643
Word-aligned transfers across a boundary . . 611
Scatter/gather . . . . . . . . . . . . . . . . . . . . . . . . 611
Linked list items . . . . . . . . . . . . . . . . . . . . . . 612
scatter/gather DMA . . . . . . . . . . . . . . . . . . . 612
Read Part Identification number . . . . . . . . . 628
Read Boot Code version number. . . . . . . . . 629
Read device serial number . . . . . . . . . . . . . 629
Compare <address1> <address2> <no of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
ISP Return Codes . . . . . . . . . . . . . . . . . . . . 630
Prepare sector(s) for write operation . . . . . . 632
Copy RAM to Flash . . . . . . . . . . . . . . . . . . . 633
Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 634
Blank check sector(s). . . . . . . . . . . . . . . . . . 634
Read part identification number . . . . . . . . . . 634
Read Boot Code version number. . . . . . . . . 635
Read device serial number . . . . . . . . . . . . . 635
Compare <address1> <address2> <no of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . 636
IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 636
Register description for signature generation 637
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
0x0x4008 4FE0). . . . . . . . . . . . . . . . . . . . . . 639
- 0x0x4008 4FE8) . . . . . . . . . . . . . . . . . . . . 639
Algorithm and procedure for signature
generation . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Signature generation . . . . . . . . . . . . . . . . . . . 640
Content verification . . . . . . . . . . . . . . . . . . . . 640
Memory Mapping Control register (MEMMAP -
0x400F C040) . . . . . . . . . . . . . . . . . . . . . . . 643
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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