LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 231

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation
Reset value: 0x0000 0003
Table 212. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description
UM10360
User manual
Bit
0
1
31:2
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
EP0
EP1
EPxx
EP31
EP23
EP15
EP7
31
23
15
7
Value
0
1
0
1
0
1
On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see
Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is
shown below.
Clear EP_RLZED bit in USBDevIntSt;
for every endpoint to be realized,
{
}
Description
Control endpoint EP0 is not realized.
Control endpoint EP0 is realized.
Control endpoint EP1 is not realized.
Control endpoint EP1 is realized.
Endpoint EPxx is not realized.
Endpoint EPxx is realized.
/* OR with the existing value of the Realize Endpoint register */
USBReEp |= (UInt32) ((0x1 << endpt));
/* Load Endpoint index Reg with physical endpoint no.*/
USBEpIn = (UInt32) endpointnumber;
/* load the max packet size Register */
USBEpMaxPSize = MPS;
/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
}
/* Clear the EP_RLZED bit */
Clear EP_RLZED bit in USBDevIntSt;
EP30
EP22
EP14
EP6
30
22
14
6
/* wait until endpoint realization is complete */
All information provided in this document is subject to legal disclaimers.
EP29
EP21
EP13
EP5
29
21
13
5
Rev. 2 — 19 August 2010
EP28
EP20
EP12
EP4
28
20
12
4
Section
Chapter 11: LPC17xx USB device controller
EP27
EP19
EP11
EP3
27
19
11
3
11.10.4.1.
EP26
EP18
EP10
EP2
26
18
10
2
EP25
EP17
EP9
EP1
25
17
UM10360
9
1
© NXP B.V. 2010. All rights reserved.
Reset value
1
1
0
EP24
EP16
231 of 840
EP8
EP0
24
16
8
0