LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 85

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 60.
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
IAB_WDT
IAB_TIMER0
IAB_TIMER1
IAB_TIMER2
IAB_TIMER3
IAB_UART0
IAB_UART1
IAB_UART2
IAB_UART3
IAB_PWM
IAB_I2C0
IAB_I2C1
IAB_I2C2
IAB_SPI
IAB_SSP0
IAB_SSP1
IAB_PLL0
IAB_RTC
IAB_EINT0
IAB_EINT1
IAB_EINT2
IAB_EINT3
IAB_ADC
IAB_BOD
IAB_USB
IAB_CAN
IAB_DMA
IAB_I2S
IAB_ENET
IAB_RIT
IAB_MCPWM
IAB_QEI
Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300)
6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300)
Function
Watchdog Timer Interrupt Active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Timer 0 Interrupt Active. See functional description for bit 0.
Timer 1. Interrupt Active. See functional description for bit 0.
Timer 2 Interrupt Active. See functional description for bit 0.
Timer 3 Interrupt Active. See functional description for bit 0.
UART0 Interrupt Active. See functional description for bit 0.
UART1 Interrupt Active. See functional description for bit 0.
UART2 Interrupt Active. See functional description for bit 0.
UART3 Interrupt Active. See functional description for bit 0.
PWM1 Interrupt Active. See functional description for bit 0.
I
I
I
SPI Interrupt Active. See functional description for bit 0.
SSP0 Interrupt Active. See functional description for bit 0.
SSP1 Interrupt Active. See functional description for bit 0.
PLL0 (Main PLL) Interrupt Active. See functional description for bit 0.
Real Time Clock (RTC) Interrupt Active. See functional description for bit 0.
External Interrupt 0 Interrupt Active. See functional description for bit 0.
External Interrupt 1 Interrupt Active. See functional description for bit 0.
External Interrupt 2 Interrupt Active. See functional description for bit 0.
External Interrupt 3 Interrupt Active. See functional description for bit 0.
ADC Interrupt Active. See functional description for bit 0.
BOD Interrupt Active. See functional description for bit 0.
USB Interrupt Active. See functional description for bit 0.
CAN Interrupt Active. See functional description for bit 0.
GPDMA Interrupt Active. See functional description for bit 0.
I
Ethernet Interrupt Active. See functional description for bit 0.
Repetitive Interrupt Timer Interrupt Active. See functional description for bit 0.
Motor Control PWM Interrupt Active. See functional description for bit 0.
Quadrature Encoder Interface Interrupt Active. See functional description for bit 0.
The IABR0 register is a read-only register that allows reading the active state of the first
32 peripheral interrupts. This allows determining which peripherals are asserting an
interrupt to the NVIC, and may also be pending if there are enabled. The remaining
interrupts can have their active state read via the IABR1 register
2
2
2
2
C0 Interrupt Active. See functional description for bit 0.
C1 Interrupt Active. See functional description for bit 0.
C2 Interrupt Active. See functional description for bit 0.
S Interrupt Active. See functional description for bit 0.
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
(Section
UM10360
© NXP B.V. 2010. All rights reserved.
6.5.10).
85 of 840