LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 227
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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Part Number:
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Manufacturer:
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Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description
Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation
Reset value: 0x0000 0000
UM10360
User manual
Bit
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
EP3RX
EP3TX
EP4RX
EP4TX
EP5RX
EP5TX
EP6RX
EP6TX
EP7RX
EP7TX
EP8RX
EP8TX
EP9RX
EP9TX
EP10RX
EP10TX
EP11RX
EP11TX
EP12RX
EP12TX
EP13RX
EP13TX
EP14RX
EP14TX
EP15RX
EP15TX
11.10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234)
EP15TX
EP11TX
EP7TX
31
23
15
Description
Endpoint 3, Isochronous endpoint.
Endpoint 3, Isochronous endpoint.
Endpoint 4, Data Received Interrupt bit.
Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 5, Data Received Interrupt bit.
Endpoint 5, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 6, Isochronous endpoint.
Endpoint 6, Isochronous endpoint.
Endpoint 7, Data Received Interrupt bit.
Endpoint 7, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 8, Data Received Interrupt bit.
Endpoint 8, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 9, Isochronous endpoint.
Endpoint 9, Isochronous endpoint.
Endpoint 10, Data Received Interrupt bit.
Endpoint 10, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 11, Data Received Interrupt bit.
Endpoint 11, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 12, Isochronous endpoint.
Endpoint 12, Isochronous endpoint.
Endpoint 13, Data Received Interrupt bit.
Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 14, Data Received Interrupt bit.
Endpoint 14, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 15, Data Received Interrupt bit.
Endpoint 15, Data Transmitted Interrupt bit or sent a NAK.
Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the
corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated
endpoint. USBEpIntEn is a read/write register.
EP15RX
EP11RX
EP7RX
30
22
14
All information provided in this document is subject to legal disclaimers.
EP14TX
EP10TX
EP6TX
29
21
13
Rev. 2 — 19 August 2010
EP14RX
EP10RX
EP6RX
28
20
12
EP13TX
EP9TX
EP5TX
Chapter 11: LPC17xx USB device controller
27
19
11
EP13RX
EP9RX
EP5RX
26
18
10
EP12TX
EP8TX
EP4TX
25
17
UM10360
9
© NXP B.V. 2010. All rights reserved.
Reset value
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
0
0
EP12RX
EP8RX
EP4RX
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