LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 799

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Index register — In some load and store instruction descriptions, the value of this
register is used as an offset to be added to or subtracted from the base register value to
form the address that is sent to memory. Some addressing modes optionally enable the
index register value to be shifted prior to the addition or subtraction. See also Base
register.
Instruction cycle count — The number of cycles that an instruction occupies the
Execute stage of the pipeline.
Interrupt handler — A program that control of the processor is passed to when an
interrupt occurs.
Interrupt vector — One of a number of fixed addresses in low memory, or in high
memory if high vectors are configured, that contains the first instruction of the
corresponding interrupt handler.
Little-endian (LE) — Byte ordering scheme in which bytes of increasing significance in a
data word are stored at increasing addresses in memory. See also Big-endian,
Byte-invariant, Endianness.
Little-endian memory — Memory in which:
See also Big-endian memory.
Load/store architecture — A processor architecture where data-processing operations
only operate on register contents, not directly on memory contents.
Memory Protection Unit (MPU) — Hardware that controls access permissions to blocks
of memory. An MPU does not perform any address translation.
Prefetching — In pipelined processors, the process of fetching instructions from memory
to fill up the pipeline before the preceding instructions have finished executing.
Prefetching an instruction does not mean that the instruction has to be executed.
Read — Reads are defined as memory operations that have the semantics of a load.
Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region — A partition of memory space.
Reserved — A field in a control register or instruction format is reserved if the field is to be
defined by the implementation, or produces Unpredictable results if the contents of the
field are not zero. These fields are reserved for use in future extensions of the architecture
or are implementation-specific. All reserved bits not used by the implementation must be
written as 0 and read as 0.
Should Be One (SBO) — Write as 1, or all 1s for bit fields, by software. Writing as 0
produces Unpredictable results.
Should Be Zero (SBZ) — Write as 0, or all 0s for bit fields, by software. Writing as 1
produces Unpredictable results.
•
•
a byte or halfword at a word-aligned address is the least significant byte or halfword
within the word at that address
a byte at a halfword-aligned address is the least significant byte within the halfword at
that address.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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