LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 274

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
13.5 Architecture
13.6 Modes of operation
UM10360
User manual
Fig 34. USB OTG controller block diagram
DMA interface
(AHB master)
(AHB slave)
interface
register
The architecture of the USB OTG controller is shown below in the block diagram.
The host, device, OTG, and I
interface. The OTG controller enables dynamic switching between host and device roles
through the HNP protocol. One port may be connected to an external OTG transceiver to
support an OTG connection. The communication between the register interface and an
external OTG transceiver is handled through an I
OTG transceiver interrupt signal.
For USB connections that use the device or host controller only (not OTG), the ports use
an embedded USB Analog Transceiver (ATX).
The OTG controller is capable of operating in the following modes:
•
•
•
USB OTG BLOCK
Host mode (see
Device mode (see
OTG mode (see
INTERFACE
INTERFACE
REGISTER
MASTER
BUS
All information provided in this document is subject to legal disclaimers.
Figure
Figure
Rev. 2 — 19 August 2010
Figure
35)
37)
2
C controllers can be programmed through the register
36)
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
DEVICE
HOST
OTG
I2C
EP_RAM
2
C interface and through the external
CONTROL
LOGIC/
PORT
MUX
ATX
Chapter 13: LPC17xx USB OTG
USB
ATX
UM10360
© NXP B.V. 2010. All rights reserved.
TRANSCEIVER
USB
port
OTG
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