LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 59
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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UM10360
User manual
4.8.3 Power-down mode
When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly
all clocks are stopped, and the DSFLAG bit in PCON is set, see
remains running and can be configured to drive the Watchdog Timer, allowing the
Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC
interrupts may be used as a wake-up source. The flash is left in the standby mode
allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The
CCLK and USBCLK clock dividers automatically get reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep Sleep mode and the logic levels of chip pins remain static.
The Deep Sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power
consumption to a very low value.
On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep
mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities
will resume after the timer expires (4 cycles). If the main external oscillator was used, the
12-bit main oscillator timer starts counting and the code execution will resume when the
timer expires (4096 cycles). The user must remember to re-configure any required PLLs
and clock dividers after the wake-up.
Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a Watchdog Timer timeout, a USB input pin transition (USB
activity interrupt), or a CAN input pin transition, when the related interrupt is enabled.
Wake-up will occur whenever any enabled interrupt occurs.
Power-down mode does everything that Deep Sleep mode does, but also turns off the
flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see
Table
before execution of code or data access in the flash memory can be accomplished.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The RTC remains running if it has been enabled and RTC interrupts may be
used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
Upon wake-up from Power-down mode, if the IRC was used before entering Power-down
mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and
expiring in 4 cycles. Code execution can then be resumed immediately following the
expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash
wake-up timer measures flash start-up time of about 100 μs. When it times out, access to
the flash is enabled. The user must remember to re-configure any required PLLs and
clock dividers after the wake-up.
Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input
pin transition, when the related interrupt is enabled.
44. This saves more power, but requires waiting for resumption of flash operation
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 4: LPC17xx Clocking and power control
Table
UM10360
44. The IRC
© NXP B.V. 2010. All rights reserved.
59 of 840
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