LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 303

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 275: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -
Table 276: UARTn Interrupt Identification Register (U0IIR - address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR -
UM10360
User manual
Bit
9
31:10 -
Bit
0
3:1
5:4
7:6
8
9
31:10 -
Symbol
ABTOIntEn
Symbol
IntStatus
IntId
-
FIFO Enable
ABEOInt
ABTOInt
0x4009 C004 when DLAB = 0) bit description
0x4009 C008) bit description
14.4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -
Value Description
010
001
011
110
0x4009 8008, U3IIR - 0x4009 C008)
The UnIIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during
an UnIIR access, the interrupt is recorded for the next UnIIR access.
Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
0
1
Value Description
0
1
Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be
determined by evaluating UnIIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the
UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below
are reserved (000,100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Copies of UnFCR[0].
End of auto-baud interrupt. True if auto-baud has finished successfully and
interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is
enabled.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
277. Given the status of UnIIR[3:0], an
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0
NA
Reset Value
1
0
NA
0
0
0
NA
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