LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 331
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description
Table 303: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description
Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description
UM10360
User manual
Bit
1
2
3
4
5
6
7
31:8
Bit
7:0
Bit
0
1
RI
DCD
-
Symbol
Delta DSR
Trailing Edge RI
Delta DCD
CTS
DSR
Symbol Description
Pad
Symbol
Start
Mode
15.4.12 UART1 Scratch Pad Register (U1SCR - 0x4001 001C)
15.4.13 UART1 Auto-baud Control Register (U1ACR - 0x4001 0020)
A readable, writable byte.
Value Description
0
1
0
1
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Value Description
0
1
0
1
0
1
This bit is automatically cleared after auto-baud completion.
Auto-baud stop (auto-baud is not running).
Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
Auto-baud mode select bit.
Mode 0.
Mode 1.
Set upon state change of input DSR. Cleared on an U1MSR read.
No change detected on modem input, DSR.
State change detected on modem input, DSR.
Set upon low to high transition of input RI. Cleared on an U1MSR read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on an U1MSR read.
No change detected on modem input, DCD.
State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U1MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U1MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected to
U1MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is connected
to U1MCR[3] in modem loopback mode.
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0
0
0
0
0
0
0
NA
0
0
Reset Value
0x00
Reset value
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