LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 294

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
13.10 Clocking and power management
UM10360
User manual
Load and enable OTG timer
/* The following assumes that the OTG timer has previously been */
/* configured for a time scale of 1 ms (TMR_SCALE = “10”)
/* and monoshot mode (TMR_MODE = 0)
/* Load the timeout value to implement the a_aidl_bdis_tmr timer */
/*
OTG_TIMER = 200;
/* Enable the timer */
OTG_STAT_CTRL |= TMR_EN;
Stop OTG timer
/* Disable the timer – causes TMR_CNT to be reset to 0 */
OTG_STAT_CTRL &= ~TMR_EN;
/* Clear TMR interrupt */
OTG_INT_CLR = TMR;
Suspend host on port 1
/* Write to PortSuspendStatus bit to suspend host port 1 –
/* this example demonstrates the low-level action software needs to take. */
/* The host stack code where this is done will be somewhat more involved. */
HC_RH_PORT_STAT1 = PSS;
The OTG controller clocking is shown in
A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.
To conserve power, the clocks to the Device, Host, OTG, and I
disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl
register. When the entire USB block is not in use, all of its clocks can be disabled by
clearing the PCUSB bit in the PCONP register.
When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.
the minimum value is 200 ms
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Figure
44.
Chapter 13: LPC17xx USB OTG
2
C controllers can be
*/
*/
*/
UM10360
© NXP B.V. 2010. All rights reserved.
*/
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