LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 570

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
28.3 Description
28.4 Register description
Table 522. Watchdog register map
UM10360
User manual
Name
WDMOD
WDTC
WDFEED
WDTV
WDCLKSEL Watchdog clock source selection register.
Description
Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.
Watchdog timer constant register. This register determines the time-out
value.
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this
register reloads the Watchdog timer with the value contained in WDTC.
Watchdog timer value register. This register reads out the current value of
the Watchdog timer.
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
and the maximum Watchdog interval is (T
The Watchdog should be used in the following manner:
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The Watchdog contains 4 registers as shown in
[1]
•
•
•
•
Set the Watchdog timer constant reload value in WDTC register.
Setup the Watchdog timer operating mode in WDMOD register.
Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
The Watchdog should be fed again before the Watchdog counter underflows to
prevent reset/interrupt.
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 28: LPC17xx Watchdog Timer (WDT)
WDCLK
Table 522
× 2
32
× 4) in multiples of (T
Access Reset
R/W
R/W
WO
RO
R/W
below.
Value
0
0xFF
NA
0xFF
0
UM10360
© NXP B.V. 2010. All rights reserved.
WDCLK
[1]
WDCLK
Address
0x4000 0000
0x4000 0004
0x4000 0008
0x4000 000C
0x4000 0010
× 256 × 4)
570 of 840
× 4).