LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 750

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.3.3.7.1 Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and
either:
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask
registers, see
not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a
late-arriving exception, the processor pushes information onto the current stack. This
operation is referred as stacking and the structure of eight data words is referred as
stack frame. The stack frame contains the following information:
Immediately after stacking, the stack pointer indicates the lowest address in the stack
frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word
address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1,
stack align adjustment is performed during stacking.
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– there is no pending exception with sufficient priority to be serviced
– the completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had
before the interrupt occurred. See
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception
entry, the stack pop is skipped and control transfers to the new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during
state saving for a previous exception, the processor switches to handle the higher
priority exception and initiates the vector fetch for that exception. State saving is not
affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late
arriving exception until the first instruction of the exception handler of the original
exception enters the execute stage of the processor. On return from the exception
handler of the late-arriving exception, the normal tail-chaining rules apply.
the processor is in Thread mode
the new exception is of higher priority than the exception being handled, in which case
the new exception preempts the original exception.
R0-R3, R12
Return address
PSR
LR.
Section
All information provided in this document is subject to legal disclaimers.
34.3.1.3.6. An exception with less priority than this is pending but is
Rev. 2 — 19 August 2010
Section 34.3.3.7.2
Chapter 34: Appendix: Cortex-M3 user guide
for more information.
UM10360
© NXP B.V. 2010. All rights reserved.
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