MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 115

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The following exceptions are recognized by the core:
The vector table pointing to these interrupts can be located at physical address 0x00000000
or 0xFFFF0000. The i.MX28 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000
to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset
(core port VINITHI =1).
The ARM 926 core includes a 16-Kbyte instruction cache and a 32-Kbyte data cache and
has two master interfaces to the AMBA AHB, as shown below.
The i.MX28 always operates in a little-endian mode.
Freescale Semiconductor, Inc.
• SWI Software interrupt
• UNDEF Undefined instruction
• PABT Instruction prefetch abort
• FIQ Fast peripheral interrupt
• IRQ Normal peripheral interrupt
• DABT Data abort
• RESET Reset
• BKPT Breakpoint
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 2-2. ARM Programmable Registers
r13 (sp)
r15 (pc)
r14 (lr)
USER
cpsr
r10
r11
r12
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r13 (sp)
r14 (lr)
spsr
FIQ
r10
r11
r12
r8
r9
r13 (sp)
r14 (lr)
spsr
IRQ
r13 (sp)
ABORT
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
SVC
r13 (sp)
r14 (lr)
spsr
undef
Chapter 2 ARM CPU Complex
115