MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 976

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SD/MMC Boot Mode
If a gate GPIO is used, then the driver will use the SD_POWER_UP_DELAY eFuse to
determine the amount of time, in 10-ms increments, to wait until starting the 1-ms
initialization sequence. This eFuse field is 6-bits wide, providing from 10–600 ms of delay.
If the field is 000000b, then the delay is a default 20 ms. If no gate GPIO is specified in
SD_POWER_GATE_GPIO, then the delay is skipped.
The SSP ports on the i.MX28 top out at 51.4 MHz with 20–40 pF loading. By default, the
serial clock is set to 12 MHz. If the SD_SPEED_ENABLE persistent bit is set, then the
driver will use a maximum speed based on the results of device identification and limited
by choices available in the SSP clock index.
For eMMC fast boot mode, serial clock is just decided by SSP_SCK_INDEX OTP bits. If
SSP_SCK_INDEX is not burned, that is invalid clock index, then ROM chooses the default
clock (12 MHz).
This mode supports the 1-bit, 4-bit, and 8-bit data MMC/SD buses. The SD_BUS_WIDTH
efuse bits selects how many bus pins are physically available for the SSP port. Bus width
will be limited based on these bits, as well as the bus width capabilities indicated by the
connected device.
The eFuse ROM0:23:22 defines one of four possible media formats, as shown in the
following table.
976
00b
01b
10b
11b
SD_MMC_MODE
MBR_MEDIA_FORMAT
RESERVED
eMMC_FASTBOOT_MEDIA_FORMAT
eSD_FASTBOOT_MEDIA_FORMAT
SD_BUS_WIDTH
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Media Format
00b
01b
10b
11b
Table 12-28. Media Formats
Reserved
Width
4-bit
1-bit
8-bit
Freescale Semiconductor, Inc.