MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2227

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Here, the DMA is instructed to perform two PIO writes prior to toggling the
DMA_PCMDKICK signal:
The DMA engine is then programmed to transfer 512-bytes to the SPDIF module.
Additionally, the SPDIF module contains a mechanism for throttling DMA requests to the
DMA engine. This circuit is programmed using the
HW_SPDIF_CTRL_DMAWAIT_COUNT field and corresponds to the number of cycles
of the apb_clk to wait before toggling the DMA_PREQ signal to the DMA engine.
There is a floor APBX frequency below which the SPDIF cannot work without errors. That
frequency can be calculated as follows:
In 16-bit Mode:
In 32-bit Mode:
(A) Ideal Calculation:
Freescale Semiconductor, Inc.
• HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_EN is set to enable interrupts on FIFO
• HW_SPDIF_FRAMECTRL_AUTO_MUTE and
• Assume that there are six other blocks apart from SPDIF on the APBX bus, and it takes
• Assume that HW_SPDIF_CTRL_DMAWAIT_COUNT is less than DMA LATENCY.
underflow detect
HW_SPDIF_FRAMECTRL_V_CONFIG are set to mute and tag the data stream as
invalid on a FIFO underflow.
four APBX clock cycles to service each block. If the number of clock cycles required
to service each block changes, change the equations accordingly.
If this is not true, then even DMA WAIT has to be added to the calculation and the
floor APBX frequency increases further.
Floor APBX freq = (DMA latency + 9) * sample rate.
For max DMA latency = (6 blocks) x (4 cycles per block) = 24 cycles and max SPDIF
sample rate = 96 kHz,
min APBX freq = 3.168 MHz.
Considering that the bandwidth requirements of the SPDIF module
are minimal (not in excess of 96 KHz) and burst requests occur
only in pairs, this field can be ignored for most, if not all,
applications.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF)
Note
2227