MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1749

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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27.3 Internal Interface Modes
The I
modes. The description and examples above explain the DMA mode. The two additional
modes are explained in the following subsections.
27.3.1 PIO Mode
The I
works similar to the DMA mode except the processor is responsible for monitoring the
HW_I2C_DEBUG0_DMAEREQ and HW_I2C_DEBUG0_DMAENDCMD pio bits. Also
the DATA_ENGINE_CMPLT_IRQ interrupt can be enabled in the block to tell the processor
when a DMA command is complete. (This is the same as the
HW_I2C_DEBUG0_DMAENDCMD event.) For example, the DMA example
256 bytes from an EEPROM
the DMA engine in DMA mode. (Be aware that the PIO_MODE bit used in previous
generation SoCs is obsolete and has been removed in this version.) To execute the example
in PIO mode the following basic steps should be followed:
10. Wait for the HW_I2C_DEBUG0_ DMAREQ bit to assert.
Freescale Semiconductor, Inc.
return 0;
1. Write to the HW_I2C_CTRL0 register with the desired field values to write the three
2. Assert the HW_I2C_CTRL0_RUN bit.
3. Wait for the HW_I2C_DEBUG0_DMAREQ bit to assert.
4. Write the word containing the 3 bytes of EEPROM slave address to the HW_I2C_DATA
5. Clear the HW_I2C_DEBUG0_DMAREQ bit.
6. Wait for the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit to assert (or the
7. Clear the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit.
8. Write the next HW_I2C_CTRL0 word.
9. Reassert the HW_I2C_CTRL0_RUN bit.
byte address to the EEPROM just as it is embedded in the DMA descriptor. Set up other
registers as needed, for example, HW_I2C_TIMING1 register.
register.
interrupt to occur).
2
2
C functionality can be programmed and managed by the i.MX28 in three different
C block on the i.MX28 supports a new PIO mode or soft-DMA mode. This mode
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
can be executed using the CPU in PIO mode instead of using
Chapter 27 Inter IC (I2C)
Reading
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