MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1284

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programming the BCH/GPMI Interfaces
read[5].dma_bar = NULL;
// 3 words sent to the GPMI
read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ)
read[5].gpmi_compare = NULL;
eccctrl
read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE);
//----------------------------------------------------------------------------
// Descriptor 7: deassert nand lock
//----------------------------------------------------------------------------
read[6].dma_nxtcmdar = NULL;
descriptor
read[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
read[6].dma_bar = NULL;
16.4.2.2 Using the Decoder
As illustrated in
1284
CS used
• DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a
• DMA descriptor 2 issues a one-byte read execute command to the NAND device that
• DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to
• DMA descriptor 5 handles the reading and error correction of the NAND data. This
NAND read setup command byte under CLE, then sends a 5-byte address under ALE.
The BCH engine is not used for these commands.
triggers its read access. The NAND then goes not ready.
remain dormant until the NAND device completes its read access time.
command's PIOs activate the BCH engine to write the read NAND data to system
memory and to process it for any errors that need to be corrected. This DMA descriptor
contains two PIO values that are system memory addresses pointing to the PAYLOAD
data area and to the AUXILIARY data area. These addresses are used by the BCH
engine's AHB master to move data into system memory and to correct it. While this
BF_APBH_CHn_CMD_WAIT4ENDCMD
Figure 16-10
BF_APBH_CHn_CMD_NANDWAIT4READY(1)
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_IRQONCMPLT
BF_APBH_CHn_CMD_CHAIN
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER);
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_SEMAPHORE
BF_APBH_CHn_CMD_NANDWAIT4READY(0)
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_IRQONCMPLT
BF_APBH_CHn_CMD_CHAIN
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER);
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BV_FLD(GPMI_CTRL0, WORD_LENGTH,
BV_FLD(GPMI_CTRL0, LOCK_CS,
BF_GPMI_CTRL0_CS
BV_FLD(GPMI_CTRL0, ADDRESS,
BF_GPMI_CTRL0_ADDRESS_INCREMENT
BF_GPMI_CTRL0_XFER_COUNT
and the sample code in
(0)
(1)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
|
8_BIT)
DISABLED)
(2)
NAND_DATA) |
(0)
(0);
// field not used but necessary to set
|
|
|
|
|
|
|
DMA Structure Code
| // wait for nand to be ready
| // need nand lock to be
|
| // follow chain to next command
// wait for command to finish before
// thread safe while turn-off BCH
// not used since this is last
// no dma transfer
// no words sent to GPMI
//
// relinquish nand lock
// BCH engine generates interrupt
// terminate DMA chain processing
|
|
|
| // must correspond to NAND
|
// no dma transfer
// field not used
// disable the ECC block
// no dma transfer
// field not used
continuing
Freescale Semiconductor, Inc.
Example: