MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2014

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
31.7.37 Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH)
This register is used in device-mode only.
endpoint flush request
Address:
Re-
2014
set
Bit
W
R
31
0
RSVD1
RSVD0
31 24
23 16
FERB
FETB
Field
Field
15 8
7 0
30
0
29
0
HW_USBCTRL_ENDPTFLUSH 8008_0000h base + 1B4h offset = 8008_01B4h
RSVD1
28
0
PERB[0] = Endpoint 0.
Reserved.
Flush Endpoint Transmit Buffer.
Writing a 1 to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a
packet is in progress for 1 of the associated endpoints, then that transfer will continue until completion.
Hardware will clear this register after the endpoint flush operation is successful.
FETB[7] = Endpoint 7.
FETB[6] = Endpoint 6.
FETB[5] = Endpoint 5.
FETB[4] = Endpoint 4.
FETB[3] = Endpoint 3.
FETB[2] = Endpoint 2.
FETB[1] = Endpoint 1.
FETB[0] = Endpoint 0.
Reserved.
Flush Endpoint Receive Buffer.
Writing a 1 to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in
progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will
clear this register after the endpoint flush operation is successful.
FERB[7] = Endpoint 7.
FERB[6] = Endpoint 6.
27
0
HW_USBCTRL_ENDPTPRIME field descriptions (continued)
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_USBCTRL_ENDPTFLUSH field descriptions
24
0
23
0
22
0
21
0
20
FETB
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
RSVD0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
FERB
0
4
3
0
0
2
0
1
0
0