MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1393

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
19.4.33 Debug Trap Control and Status for AHB Layer 0 and 3
The Debug Trap Register provides control and status information for the trap functionality.
HW_DIGCTL_DEBUG_TRAP: 0x2B0
Freescale Semiconductor, Inc.
Reset
Reset
CACHE_SS
VALID_SS
DRTY_SS
Bit
Bit
DTAG_SS
W
W
ITAG_SS
R
R
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
31 18
17 16
15 14
13 12
11 10
Field
9 8
7 6
5 4
3 2
1 0
31
15
0
0
RSVD3
HW_DIGCTL_ARMCACHE
C2A0h
(HW_DIGCTL_DEBUG_TRAP)
30
14
0
0
Reserved.
Timing control for 64x24x1 RAMs (both instruction and data cache_valid arrays).
Reserved.
Timing control for 128x8x1 RAM (DDRTY).
Reserved.
Timing Control for 1024x32x4 RAMs (both instruction and data cache arrays).
Reserved.
Timing Control for 256x22x4 RAM (DTAG).
Reserved.
Timing Control for 128x22x4 RAM (ITAG).
DRTY_SS
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DIGCTL_ARMCACHE field descriptions
28
12
0
0
27
11
0
0
RSVD2
8001_C000h base + 2A0h offset = 8001_
26
10
0
0
CACHE_SS
25
0
0
9
RSVD4
24
0
0
8
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
23
0
0
7
RSVD1
22
0
0
6
DTAG_SS
21
0
5
0
20
0
4
0
19
0
0
3
RSVD0
18
0
0
2
VALID_SS
17
ITAG_SS
0
0
1
1393
16
0
0
0