MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1950

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
30.4.6 UART Interrupt Register (HW_UARTAPP_INTR)
HW_UARTAPP_INTR: 0x050
HW_UARTAPP_INTR_SET: 0x054
HW_UARTAPP_INTR_CLR: 0x058
HW_UARTAPP_INTR_TOG: 0x05C
1950
Reset
BAUD_DIVFRAC
BAUD_DIVINT
Bit
W
R
RSVD1
31 16
15 14
RSVD
WLEN
STP2
Field
13 8
SPS
FEN
EPS
PEN
6 5
7
4
3
2
1
0
15
0
RSVD
14
0
Baud Rate Integer [15:0]. The integer baud rate divisor.
Reserved, do not modify, read as zero.
Baud Rate Fraction [5:0]. The fractional baud rate divisor.
Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked
as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
bit is cleared stick parity is disabled.
Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as
follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits.
Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When
cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding
registers.
Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive
logic does not check for two stop bits being received.
Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission
and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd
parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by
Parity Enable (PEN, bit 1) being cleared to 0.
Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no
parity bit added to the data frame.
Reserved, do not modify, read as zero.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_UARTAPP_LINECTRL2 field descriptions
12
0
BAUD_DIVFRAC
11
0
10
0
0
9
0
8
Description
SPS
0
7
0
6
WLEN
5
0
FEN
4
0
Freescale Semiconductor, Inc.
STP2
0
3
EPS
0
2
PEN
0
1
RSVD1
0
0