MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1305

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

16.6.16 Hardware BCH ECC Debug Register0 (HW_BCH_DEBUG0)
The hardware BCH accelerator internal state machines and signals can be seen in the ECC
debug register.
HW_BCH_DEBUG0: 0x100
HW_BCH_DEBUG0_SET: 0x104
HW_BCH_DEBUG0_CLR: 0x108
HW_BCH_DEBUG0_TOG: 0x10C
The HW_BCH_DEBUG0 register provides access to various internal state information
which might prove useful during hardware debug and validation.
EXAMPLE
// perform BIST operation
HW_BCH_DEBUG0_CLR(BM_BCH_DEBUG0_ROM_BIST_ENABLE | BM_BCH_DEBUG0_ROM_BIST_COMPLETE);
Freescale Semiconductor, Inc.
bist status
DATAN_SIZE
HW_BCH_DEBUG0_SET(BM_BCH_DEBUG0_ROM_BIST_ENABLE);
// poll until BIST_DONE
while( (HW_BCH_DEBUG0_RD() & BM_BCH_DEBUG0_ROM_BIST_COMPLETE) == 0 );
i=HW_BCH_DBGKESREAD();
if(HW_BCH_DBGKESREAD_RD() != 0x7AA3792F) {
}
// BIST FAILED
err++;
Field
11 0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size
MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size
for block 0, which is important when metadata is stored separately or for balancing the amount of data stored
in each block.
HW_BCH_FLASH3LAYOUT1 field descriptions (continued)
ECC2 — ECC 2 to be performed
ECC4 — ECC 4 to be performed
ECC6 — ECC 6 to be performed
ECC8 — ECC 8 to be performed
ECC10 — ECC 10 to be performed
ECC12 — ECC 12 to be performed
ECC14 — ECC 14 to be performed
ECC16 — ECC 16 to be performed
ECC18 — ECC 18 to be performed
ECC20 — ECC 20 to be performed
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
// enable BIST operation
// clear
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