MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1588

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
This register allows any number of a range of 32 message buffer interrupts to be enabled
or disabled. It contains one interrupt mask bit per buffer, enabling the ARM to determine
which buffer generates an interrupt after a successful transmission or reception (that is,
when the corresponding IFLAG2 bit is set).
Address:
Re-
25.6.10 Interrupt Masks 1 Register (HW_CAN_IMASK1)
The default value of this register is 0x00000000.
This register enables or disables any number of a range of 32 message buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the ARM to determine which buffer
generates an interrupt after a successful transmission or reception (that is, when the
corresponding IFLAG1 bit is set)
Address:
Re-
25.6.11 Interrupt Flags 2 Register (HW_CAN_IFLAG2)
The default value of this register is 0x00000000.
1588
set
set
Bit
Bit
W
W
R
R
31
31
0
0
BUFM
BUFM
Field
31 0
Field
31 0
30
30
0
0
29
29
0
0
HW_CAN_IMASK2
HW_CAN_IMASK1
28
28
0
0
Each bit enables or disables the respective FlexCAN message buffer interrupt (message buffers 32~63).
This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
8003_2000h base + 24h offset = 8003_2024h
8003_2000h base + 28h offset = 8003_2028h
HW_CAN_IMASK2 field descriptions
HW_CAN_IMASK1 field descriptions
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
BUFM
BUFM
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0