MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1983

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

31.7.18 USB Status Register (HW_USBCTRL_USBSTS)
This register indicates various states of the Host/Device Controller and any pending
interrupts. This register does not indicate status resulting from a transaction on the serial
bus. Software clears certain bits in this register by writing a 1 to them. * Default
Value:0x00001000 (Host mode), 0x00000000 (Device mode)
Freescale Semiconductor, Inc.
Field
RST
RS
1
0
010b = 256_ELEMENTS (1024 bytes).
011b = 128_ELEMENTS (512 bytes).
100b = 64_ELEMENTS (256 bytes).
101b = 32_ELEMENTS (128 bytes).
110b = 16_ELEMENTS (64 bytes).
111b = 8_ELEMENTS (32 bytes).
Only the host controller uses this field.
Controller Reset (RESET).
Software uses this bit to reset the controller. This bit is set to 0 by the Host/Device Controller when the reset
process is complete. Software cannot terminate the reset process early by writing a 0 to this register.
Host Controller: When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers,
counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a 1 when the
HCHalted bit in the USBSTS register is a 0. Attempting to reset an actively running host controller will result
in undefined behavior.
Device Controller: When software writes a 1 to this bit, the Device Controller resets its internal pipelines,
timers, counters, state machines etc. to their initial value. Writing a 1 to this bit when the device is in the
attached state is not recommended, since the effect on an attached host is undefined. In order to ensure
that the device is not in an attached state before initiating a device controller reset, all primed endpoints
should be flushed and the USBCMD Run/Stop bit should be set to 0.
Run/Stop (RS).
Default 0.
1 = Run.
0 = Stop.
Host Controller: When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host
Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller
completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates
when the Host Controller has finished the transaction and has entered the stopped state. Software should
not write a 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the USBSTS
register is a 1).
Device Controller: Writing a 1 to this bit will cause the device controller to enable a pullup on D+ and initiate
an attach event. This control bit is not directly connected to the pullup enable, as the pullup will become
disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event
before the device controller has been properly initialized. Writing a 0 to this will cause a detach event.
HW_USBCTRL_USBCMD field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
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