MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2266
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Operation
38.2.4 Delay Channels
To minimize the interrupt load on the ARM processor, four delay channels are provided.
Each has an 11-bit counter that increments at 2 KHz. A delay channel can be kicked off
either by an ARM store instruction or at the completion of a delay channel time-out. At
time-out, each channel has the option of kicking off any combination of LRADC conversions,
as well as any combination of delay channels.
Consider the case of a touch-screen that requires 4x oversampling of its coordinate values.
Further, suppose you wish to receive an oversampled X or Y coordinate approximately
every 5 ms and that the oversampling should be spaced at 1-ms intervals.
2266
• In the touch-screen, first select either X or Y drive, then set up the appropriate LRADC.
• In setting up the LRADC, clear the accumulator associated with it by setting the
• Next, set up two delay channels.
ACCUMULATE bit and set the NUM_SAMPLES field to 3 (4 samples before interrupt
request).
• Delay Channel 1 is set to delay 1 ms (DELAY = 1, two ticks) and then kick the
• Delay Channel 0 is set to delay 1 ms with LOOP_COUNT = 0, that is, one time.
schedule bit for LRADC 4. Its LOOP_COUNT bit field is also set to 3, so that four
kicks of LRADC 4 occur, each spaced by 1 ms.
Its TRIGGER_DELAYS field is set to trigger Delay Channel 1 when it times out.
The ISR routine kicks off Delay Channel 0 immediately before it does its return
from interrupt. Another interrupt (LRADC4_IRQ) is asserted once the entire 4x
oversample data capture is complete. A sample timeline for such a sequence is
shown in
The DELAY fields in HW_LRADC_DELAY0,
HW_LRADC_DELAY1, HW_LRADC_DELAY2, and
HW_LRADC_DELAY3 must be non-zero; otherwise, the LRADC
will not trigger the delay group. The ACCUMULATE bit in the
appropriate channel register HW_LRADC_CHn must be set to 1
if NUM_SAMPLES is greater then 0; otherwise, the IRQs will
not fire.
Figure
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
38-3.
Note
Freescale Semiconductor, Inc.
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