MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 152

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
5.4.4 Interrupt Collector Interrupt Vector Base Address Register
This register is used by the priority logic to generate a unique vector address for each of
the 80 interrupt request lines coming into the interrupt collector. The vector address is
formed by multiplying the interrupt bit number by 4 and adding it to the vector base address.
HW_ICOLL_VBASE: 0x040
HW_ICOLL_VBASE_SET: 0x044
HW_ICOLL_VBASE_CLR: 0x048
HW_ICOLL_VBASE_TOG: 0x04C
This register provides a mechanism to specify the base address of the interrupt vector table.
It is used in the computation of the value supplied in HW_ICOLL_VECTOR register.
EXAMPLE
HW_ICOLL_VBASE_WR(pInterruptVectorTable);
Address:
152
Reset
FIQ_FINAL_
IRQ_FINAL_
Bit
W
RSRVD1
ENABLE
ENABLE
R
Field
15 0
17
16
31
0
(HW_ICOLL_VBASE)
HW_ICOLL_VBASE
30
0
Set this bit to one to enable the final FIQ output to the CPU. Set this bit to zero for testing the interrupt
collector without causing actual CPU interrupts.
0x0
0x1
Set this bit to one to enable the final IRQ output to the CPU. Set this bit to zero for testing the interrupt
collector without causing actual CPU interrupts.
0x0
0x1
Always write zeroes to this bitfield.
29
0
DISABLE — Disable
ENABLE — Enable
DISABLE — Disable
ENABLE — Enable
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ICOLL_CTRL field descriptions (continued)
28
0
8000_0000h base + 40h offset = 8000_0040h
27
0
26
0
TABLE_ADDRESS[31:16]
25
0
24
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0