MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 852

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Clock Frequency Management
3 output clocks repeats
every 8 reference clocks
CLK_REF
3 bit divider
0.000 0.011 0.110 1.001 0.100 0.111 1.010 0.101 1.000 0.011
CLK_OUT
nd
2
cycle on falling clk_ref
½ cycle shift
Figure 10-2. Fractional Clock divide; 3/8 example
10.3.3 Gated Clock Divide Mode
This mode is selected when the reference clock frequency is divided by a range of 1 < div
< 2. To select this mode, program the FRAC_EN field to logic 1 and progarm the DIV field
with the most significant bit set to logic 1. In this case, the reference clock is enabled/disabled
on a cycle by cycle basis to pass to the output clock domain. Essentially, the reference clock
is gated on or off depending on the carry out bit of the fractional count accumulator. This
option is useful to divide the 24 MHz clock to a range between 12 to 24 MHz. The effective
period is equal to the reference period since the output clock is a gated version of the
reference clock. For example, a divide value of 4/3 will allow three consecutive pulses of
the reference clock to propagate and will then gate off a single reference clock cycle. The
edge to edge timing is effectively equal to the reference clock.
Output clock period
equal to reference clock.
CLK_REF
CLK_OUT
3 output clocks for every
4 reference clocks.
Figure 10-3. Divide Range 1 < div < 2
10.4 Clock Frequency Management
Clock frequency selection for some domains can be a function of multiple reference clock
sources and divide parameters that are set in the CLKCTRL PIO control registers. The most
extreme case is using a programmable fractional PLL clock divider, a multiplexer that
selects either the xtal clock or fractional PLL clock as a source to drive the CLKCTRL
divider, and the divide value for the CLKCTRL divider itself. When programming a selected
frequency, the sequence of events to achieve a given frequency must maintain the integrity
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
852
Freescale Semiconductor, Inc.