MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1807
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1807 of 2327
- Download datasheet (17Mb)
29.3 Switch Configuration
29.3.1 Overview
The Switch Core is designed to be seamlessly connected to the MorethanIP ENET-MAC
Core and DMA controllers. For control and configuration, the switch implements an APB
Register interface and multiple maskable interrupts.
Freescale Semiconductor, Inc.
• All descriptions related to switch functions refer to the switch
• Receive Frame buffer (DMA0 TX interface). Can hold at
• Decoupling buffer only (DMA0 RX interface) to absorb
• The APB Host Interface module implements an indirect
mode connected to the DMA RX. If the switch is enabled
these are driven by the switch internal transmit interfaces.
See 4 page 26 for a description of the operational modes.
internal receive/transmit interfaces.
least one complete frame transferred from DMA0 to the
switch. This is a local 64-bit wide FIFO to absorb a burst
from the DMA, provide the necessary transaction handshake
to the DMA, and forward the frame then to the switch logic.
switch latency (for example, 16/32 words) resulting from a
rdy deassertion from DMA0.
addressing scheme to the internal registers to allow arbitrary
length access cycles (such as address table read/write and
configuration register read/write). However, the DMA control
registers are directly mapped and accessed through APB.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
1807
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