MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1270

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Programming the BCH/GPMI Interfaces
1270
6. Issue NAND status command byte (under CLE).
7. Read the status and compare against expected.
8. If status is incorrect or incomplete, branch to error handling descriptor chain.
9. Otherwise, write is complete and emit GPMI interrupt.
HW_GPMI_COMPARE
HW_GPMI_ECCCTRL
HW_GPMI_CTRL0
CMD
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
<=
<=
<=
<=
command_mode
xfer_count
Figure 16-7. BCH DMA Descriptor Legend
Start GPMI DMA chain for next write or read transfer.
Return and wait for DMA channel 4 (or 5 or 6 or 7)
Point the GPMI DMA channel 4 (or 5 or 6 or 7) at
HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0
Figure 16-6. BCH Encode Flowchart
Run the prescribe initialization sequence.
the prescribed static DMA sequence.
word_length
cmdwords
ecc_cmd
command complete interrupt.
APBH DMA CH4 Command
mask
BCH ENCODE &
Start the DMA.
WRITE NAND
Complete ISR
wait4endcmd
lock_cs
STOP
STOP
HW_GPMI_ECCCOUNT
HW_GPMI_AUXILIARY
HW_GPMI_PAYLOAD
NEXT CMD ADDR
Descriptor Legend
BUFFER ADDR
semaphore
CS
nandwait4ready
address
enable_ecc
Must use SCT clear
address_increment
nandlock
reference
irqoncmplt chain command
Freescale Semiconductor, Inc.
xfer_count
buffer_mask

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