MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1285

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

As the BCH block receives data from the GPMI:
As the BCH decoder reads the data and parity blocks, it records a special condition, i.e.,
that all of the bits of a payload data block or metadata block are one, including any associated
parity bytes. The all-ones case for both parity and data indicates an erased block in the
NAND device.
The HW_BCH_STATUS0 register contains a 4-bit field that indicates the final status of
the auxiliary block. A value of 0x0 indicates no errors found for a block.
Recall that up to four NAND devices can have DMA chains in-flight at once, i.e. they can
all be contending for access to the GPMI data bus. It is impossible to predict which NAND
device will enter the BCH engine with a transfer first, because each chain includes a
wait4ready command structure. As a result, firmware should look at the
HW_BCH_STATUS0_COMPLETED_CE bit field to determine which block is being
Freescale Semiconductor, Inc.
• DMA descriptor 6 disables the BCH engine with the NANDLOCK asserted. This is
• DMA descriptor 7 deasserts the NANDLOCK to free up the GPMI resource to another
• The decoder transforms the read NAND data block into a BCH code word and computes
• If no errors are present, then the BCH block can immediately report back to firmware.
• If an error is present, then the BCH block corrects the necessary data block or parity
• A value of 1 to 20 inclusive indicates that many correctable errors were found and fixed.
• A value of 0xFE indicates uncorrectable errors detected on the block.
• A value of 0xFF indicates that the block was in the special ALL ONES state and is
• All other values are disallowed by the hardware design.
example is reading an entire 4K page payload plus metadata it is equally possible
to read just one 512-byte payload block or just the uniquely protected metadata block
in a single 7 DMA structure transfer.
necessary to ensure that the GPMI resource is not arbitrated to another DMA channel
when multiple DMA channels are active concurrently.
channel.
the codeword syndrome.
This report is passed as the HW_BCH_CTRL_COMPLETE_IRQ interrupt status bit
and the associated status registers in HW_BCH_STATUS0/1 registers.
block bytes, if possible (not all errors are correctable).
therefore considered to be an ERASED block.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
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