MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2150

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
2150
Reset
Reset
INTERLACED_
INTERLACED_
CLKGATE
Bit
Bit
W
W
OUTPUT
SFTRST
R
R
HW_PXP_CTRL_SET(BM_PXP_CTRL_SFTRST);
HW_PXP_CTRL_CLR(BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE);
RSVD2
INPUT
29 28
27 26
25 24
Field
31
30
31
15
1
0
HW_PXP_CTRL
S0_FORMAT
30
14
1
0
Set this bit to zero to enable normal PXP operation. Set this bit to one (default) to disable clocking with the
PXP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the PXP
block to its default state.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
Reserved, always set to zero.
Determines how the PXP writes it's output data. Output interlacing should not be used in conjunction with
input interlacing. Splitting frames into fields is most efficient using output interlacing. 2-plane output formats
AND interlaced output is NOT supported.
0x0
0x1
0x2
0x3
When set, causes the fetch side of the PXP to fetch every other line from the source buffers. This effectively
produces one field of interlaced output data. Scaling should NOT be enabled for interlaced operation and
only overlays with boundaries on 8x16 multiples are supported.
29
13
0
0
RSVD2
PROGRESSIVE — All data written in progressive format to the OUTBUF Pointer.
FIELD0 — Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
FIELD1 — Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
INTERLACED — Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written
to OUTBUF2.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
8002_A000h base + 0h offset = 8002_A000h
HW_PXP_CTRL field descriptions
27
11
0
0
26
10
0
0
25
0
ROTATE
0
9
24
0
0
8
Description
23
0
0
7
OUTBUF_FORMAT
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0