MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2076

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
signal of the interface (called CCIRCLK here for uniqueness). CCIRCLK also can be
obtained on the LCD_DOTCK pin. The mode shares the write FIFO with the LCD interface
and the associated pipeline. The programmable parameters in registers
HW_LCDIF_DVICTRL0-3 allow setting the total number of horizontal lines per frame,
vertical and horizontal blanking interval, odd and even field start and end positions, and so
on. In short, these parameters are provided to ensure that the hardware has enough flexibility
to generate the right 525/60 or 625/50 data streams. Most of the initialization steps in
Initializing the LCDIF
also. The register descriptions in the programmable registers section at the end of this chapter
include example code for programming the DVICTRL0-3 registers.
In DVI mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the
current transfer, the software should make the DVI_MODE bit the value 0, so that all data
that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer is
complete, the block will automatically clear the RUN bit and assert the cur_frame_done
interrupt.
33.2.10 LCDIF Pin Usage by Interface Mode
The following table shows the pin usage for all of the supported modes when the PINCTRL
registers are programmed for LCD functionality. See
a more complete description of pin multiplexing options and how to program each pin
individually.
The VSYNC signal has been mapped onto two pins, LCD_BUSY and LCD_VSYNC. The
pin multiplexing can be programmed to select either of those pins to function as VSYNC.
2076
Figure 33-14. LCDIF Interface Signals in ITU-R BT.656 Digital Video Interface Mode
There is an option to internally mux the HSYNC, DOTCLK and
ENABLE signals in the DOTCLK mode by setting the
F
F
Start of Digital Line
EAV Code
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
4
0
0
X
Y
such as data shifting, swizzle, and so on, are applicable to DVI mode
8
0
1
0
8
0
268 (280)
Blanking
1
0
1716 (1728)
8
0
1
0
F
F
NOTE
SAV Code
0
0
4
0
0
X
Y
Start of Digital Active Line
C
B
H ControlSignal
Co-Sited
Y
C
R
Pin Control and GPIO Overview
Y
B
C
Co-Sited
1440
Y
C
R
Y
B
C
Freescale Semiconductor, Inc.
Y
F
F
Next Line
Stream
Digital
Video
for