MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1245

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 15 General-Purpose Media Interface(GPMI)
15.2.6 Hardware BCH Interface
The GPMI provides an interface to the BCH module. This reduces the SOC bus traffic and
the software involvement. When in BCH mode, parity information is inserted on-the-fly
during writes to 8-bit NAND devices. The BCH will supply payload and parity to the GPMI
to write to the NAND. During NAND reads, parity is checked and ECC processing is
performed after each read block. In this case, the GPMI reads the NAND device and redirects
the data and parity to the BCH module for ECC processing.
To program the BCH for NAND writes, remove the soft reset and clock gates from
HW_BCH_CTRL_SFTRST and HW_BCH_CTRL_CLKGATE. The bulk of BCH
programming is actually applied to the GPMI through PIO operations embedded in its DMA
command structures. This has a subtle implication when writing to the GPMI ECC registers:
access to these registers must be written in a progressive register order. Therefore, to write
to the HW_GPMI_ECCCOUNT register, write first (in order) to registers
HW_GPMI_CTRL0, HW_GPMI_COMPARE, and HW_GPMI_ECCCTRL before writing
to HW_GPMI_ECCCOUNT. These additional register writes need to be accounted for in
the CMDWORDS field of the respective DMA channel command register. See the descriptive
text, flowcharts, and code examples in
Programming the BCH/GPMI Interfaces
for more
information about using GPMI registers to program the ECC function.
The HW_GPMI_PAYLOAD and HW_GPMI_AUXILIARY pointers need to be
word-aligned for proper ECC operation. If those pointers are non-word-aligned, then the
BCH engine will not operate properly and could possibly corrupt system memory in the
adjoining memory regions.
15.3 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
for additional information on using the SFTRST and
CLKGATE bit fields.
15.4 Programmable Registers
GPMI Hardware Register Format Summary
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1245