MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 506

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
506
8002_41C0
8002_41D0
8002_42C0
8002_42D0
8002_41A0
8002_41B0
8002_41E0
8002_41F0
8002_4200
8002_4210
8002_4220
8002_4230
8002_4240
8002_4250
8002_4260
8002_4270
8002_4280
8002_4290
8002_42A0
8002_42B0
8002_42E0
Absolute
address
(hex)
APBX DMA Channel 1 Buffer Address Register
(HW_APBX_CH1_BAR)
APBX DMA Channel 1 Semaphore Register
(HW_APBX_CH1_SEMA)
AHB to APBX DMA Channel 1 Debug Information
(HW_APBX_CH1_DEBUG1)
AHB to APBX DMA Channel 1 Debug Information
(HW_APBX_CH1_DEBUG2)
APBX DMA Channel 2 Current Command Address Register
(HW_APBX_CH2_CURCMDAR)
APBX DMA Channel 2 Next Command Address Register
(HW_APBX_CH2_NXTCMDAR)
APBX DMA Channel 2 Command Register
(HW_APBX_CH2_CMD)
APBX DMA Channel 2 Buffer Address Register
(HW_APBX_CH2_BAR)
APBX DMA Channel 2 Semaphore Register
(HW_APBX_CH2_SEMA)
AHB to APBX DMA Channel 2 Debug Information
(HW_APBX_CH2_DEBUG1)
AHB to APBX DMA Channel 2 Debug Information
(HW_APBX_CH2_DEBUG2)
APBX DMA Channel 3 Current Command Address Register
(HW_APBX_CH3_CURCMDAR)
APBX DMA Channel 3 Next Command Address Register
(HW_APBX_CH3_NXTCMDAR)
APBX DMA Channel 3 Command Register
(HW_APBX_CH3_CMD)
APBX DMA Channel 3 Buffer Address Register
(HW_APBX_CH3_BAR)
APBX DMA Channel 3 Semaphore Register
(HW_APBX_CH3_SEMA)
AHB to APBX DMA Channel 3 Debug Information
(HW_APBX_CH3_DEBUG1)
AHB to APBX DMA Channel 3 Debug Information
(HW_APBX_CH3_DEBUG2)
APBX DMA Channel 4 Current Command Address Register
(HW_APBX_CH4_CURCMDAR)
APBX DMA Channel 4 Next Command Address Register
(HW_APBX_CH4_NXTCMDAR)
APBX DMA Channel 4 Command Register
(HW_APBX_CH4_CMD)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBX memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
7.5.16/533
7.5.17/534
7.5.18/535
7.5.19/537
7.5.20/537
7.5.21/538
7.5.22/538
7.5.23/540
7.5.24/541
7.5.25/541
7.5.26/544
7.5.27/544
7.5.28/545
7.5.29/545
7.5.30/547
7.5.31/548
7.5.32/548
7.5.33/551
7.5.34/551
7.5.35/552
7.5.36/552
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