EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 122
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–18
Figure 5–14. Clock Input Multiplexer Logic for Arria II GX PLLs
Notes to
(1) Input clock multiplexing is controlled through a configuration file (.sof or .pof) only; it cannot be dynamically controlled when the device is
(2) Dedicated clock input pins to the PLLs: n=4 for PLL_4; n=4 or 8 for PLL_3; n=8 or 12 for PLL_2; and n=12 for PLL_1.
(3) You can drive the GCLK or RCLK clock input with an output from another PLL, a pin-driven GCLK or RCLK, or through a clock control block,
Figure 5–15. Clock Input Multiplexer Logic for Arria II GZ devices
Notes to
(1) When the device is operating in user mode, input clock multiplexing is controlled through a configuration file
(2) n=0 for L2 and L3 PLLs; n=4 for B1 and B2 PLLs; n=8 for R2 and R3 PLLs, and n=12 for T1 and T2 PLLs.
(3) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a clock control block provided
Arria II Device Handbook Volume 1: Device Interfaces and Integration
operating in user mode.
provided the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK or RCLK. An internally generated global
signal or general purpose I/O pin cannot drive the PLL.
(.sof or .pof) only and cannot be dynamically controlled.
the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK or RCLK. An internally generated global signal or
general purpose I/O pin cannot drive the PLL.
Figure
Figure
5–14:
5–15:
f
GCLK / RCLK input (3)
For more information about the clock control block and its supported features in the
Quartus II software, refer to the
Guide.
Adjacent PLL output
GCLK / RCLK input (3)
Adjacent PLL output
CLK[n+3..n] (2)
clk[n+3..n] (2)
4
4
4
4
Clock Control Block (ALTCLKCTRL) Megafunction User
(1)
(1)
(1)
(1)
inclk0
inclk1
inclk0
inclk1
Chapter 5: Clock Networks and PLLs in Arria II Devices
To the clock
switchover block
To the clock
switchover block
December 2010 Altera Corporation
Clock Networks in Arria II Devices
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