EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 269

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
Figure 8–24. Center PLLs Driving DPA-Enabled Differential I/Os
December 2010 Altera Corporation
1
Using Both Center PLLs
You can use center PLLs to drive DPA-enabled channels simultaneously, if they drive
these channels in their adjacent banks only, as shown in
Center PLLs are available at the right I/O banks of Arria II GX devices and the right
and left I/O banks of Arria II GZ devices.
If one of the center PLLs drives the DPA-enabled channels in the upper and lower I/O
banks, you cannot use the other center PLL for DPA-enabled channels, as shown in
Figure
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
CLK
CLK
PLL
PLL
8–24.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Diff I/O
Diff I/O
Center
CLK
CLK
Figure
PLL
PLL
8–23.
Unused
PLL
8–29