EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 139
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–29. Delay Insertion with VCO Phase Output and Counter Delay Time for Arria II Devices
December 2010 Altera Corporation
CLK0
CLK1
CLK2
135
180
225
270
315
45
90
0
1/8 t
VCO
Equation 5–2
the start of the counters for a predetermined number of counter clocks.
Equation 5–2. Coarse-Resolution Phase Shifts for Arria II Devices
where C is the count value set for the counter delay time, (this is the initial setting in
the “PLL usage” section of the compilation report in the Quartus II software). If the
initial value is 1, C – 1 = 0° phase shift.
Figure 5–29
the VCO phase taps method. The eight phases from the VCO are shown and labeled
for reference. For this example, CLK0 is based off the 0phase from the VCO and has the
C value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based off the
135× phase tap from the VCO and also has the C value for the counter set to one. The
CLK1 signal is also divided by four. In this case, the two clocks are offset by 3
CLK2 is based off the 0phase from the VCO but has the C value for the counter set to
three. This arrangement creates a delay of 2
Use the coarse- and fine-phase shifts to implement clock delays in Arria II devices.
The ALTPLL megafunction allows you to enter the desired VCO phase taps and initial
counter value settings through the MegaWizard
software.
Arria II devices support dynamic phase-shifting of VCO phase taps only. The phase
shift is reconfigurable any number of times and each phase shift takes about one
SCANCLK cycle, allowing you to implement large phase shifts quickly.
t
d0-1
t
d0-2
shows an example of a phase-shift insertion with the fine resolution with
shows the coarse-resolution phase shifts are implemented by delaying
t
VCO
Φ
coarse
Arria II Device Handbook Volume 1: Device Interfaces and Integration
=
C − 1
f
V
co
Φ
COARSE
=
(C − 1)N
™
Mf
Plug-In Manager in the Quartus II
REF
(two complete VCO periods).
Φ
fine
.
5–35
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