EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 236
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–40
Figure 7–27. IOE Output and Output Enable Path Registers for Arria II GX Devices
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) The write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
7–27:
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, and the third register aligns the
captured data. You can choose to use the same clock for the positive edge and
negative edge registers, or two complementary clocks (DQS/CQ for positive-edge
register and DQSn/CQn for negative-edge register). The third register that aligns the
captured data uses the same clock as the positive edge registers.
For Arria II GX devices, the resynchronization registers resynchronize the data to the
resynchronization clock domain. These registers are clocked by the resynchronization
clock that is generated by the PLL. The outputs of the resynchronization registers go
straight to the core.
For Arria II GZ devices, the resynchronization registers resynchronize the data to the
system clock domain. These registers are clocked by the resynchronization clock that
is generated by the PLL. The outputs of the resynchronization registers can go straight
to the core or to the HDR blocks, which are clocked by the divided-down
resynchronization clock.
Figure 7–27
paths. The device can bypass each block of the output and output enable path.
OE
From core
datahi
From core
datainlo
From core
Write
Clock (2)
shows the registers available in the Arria II GX output and output enable
Double Data Rate Output-Enable Registers
Output Reg Bo
Output Reg Ao
OE Reg B
OE Reg A
Double Data Rate Output Registers
D
D
D
D
DFF
DFF
DFF
DFF
Q
Q
Q
Q
OE
OE
1
0
dataout
OR2
Chapter 7: External Memory Interfaces in Arria II Devices
dataout
TRI
(Note 1)
Arria II External Memory Interface Features
DQ or DQS
December 2010 Altera Corporation
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