EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 75

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II Devices
DSP Block Overview
Table 4–1. Number of DSP Blocks in Arria II Devices
Figure 4–1. Overview of DSP Block Signals
December 2010 Altera Corporation
Arria II GX
Arria II GZ
Note to
(1) The numbers in this table represents the numbers of multipliers in their respective mode.
Family
Table
Control
4–1:
Input
Data
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
Device
288
Table 4–1
Each DSP block occupies four logic array blocks (LABs) in height and you can divide
further into two half blocks that share some common clocks signals, but are for all
common purposes identical in functionality.
block.
100
115
130
29
39
56
72
82
92
144
144
34
lists the number of DSP blocks in Arria II devices.
Multipliers
1,040
9 × 9
232
312
448
576
656
736
800
920
Independent Input and Output Multiplication Operators
Full-DSP Block
Multipliers
12 × 12
(Note 1)
174
234
336
432
492
552
600
690
780
Half-DSP Block
Half-DSP Block
Multipliers
Arria II Device Handbook Volume 1: Device Interfaces and Integration
18 × 18
116
156
224
288
328
368
400
460
520
Figure 4–1
Complex
18 × 18
112
144
164
184
200
230
260
58
78
shows the layout of each
Multipliers
72
36 × 36
72
112
144
164
184
200
230
260
58
78
Multipliers
Multiplier
Output
Data
Output
Data
Precision
18 × 36
Adder
Mode
High
116
156
224
288
328
368
400
460
520
Multipliers
Multiplier
4–3
18 × 18
Adder
Mode
1,040
Four
232
312
448
576
656
736
800
920