EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 591
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
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Chapter 4: Reset Control and Power Down in Arria II Devices
Dynamic Reconfiguration Reset Sequences
Dynamic Reconfiguration Reset Sequences
Figure 4–11. Reset Sequence in Basic ×1 Mode with the Receiver CDR in Automatic Lock Mode (TX Option)
December 2010 Altera Corporation
Reset Sequence with Data Rate Division in the TX Option
Reset and Control Signals
Output Status Signals
1
rate_switch_ctrl[1:0]
You can configure the Arria II GX or GZ device in ×1, ×2, ×4, and ×8 PIPE lane
configurations. The reset sequence described in
applies to all these multi-lane configurations.
When using dynamic reconfiguration in data rate divisions in TX or Channel and TX
CMU PLL select/reconfig modes, use the following reset sequences.
Use the example reset sequence shown in
dynamic reconfiguration controller to change the data rate of the transceiver channel.
In this example, dynamic reconfiguration is used to dynamically reconfigure the data
rate of the transceiver channel configured in Basic ×1 mode with the receiver CDR in
automatic lock mode.
As shown in
dynamic reconfiguration controller to change the configuration of the transmitter
channel:
1. After power up and properly establishing that the transmitter is operating
2. Assert the tx_digitalreset signal.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. After the completion of dynamic reconfiguration, the busy signal is de-asserted
5. Finally, tx_digitalreset can be de-asserted to continue with the transmitter
tx_digitalreset
correctly, write the new value for the data rate in the appropriate register (in this
example, rate_switch_ctrl[1:0]) and subsequently assert the write_all signal
(marker 1) to initiate the dynamic reconfiguration.
f
execute its operation, as indicated by the assertion of the busy signal (marker 2).
(marker 3).
operation (marker 4).
write_all
busy
For more information, refer to
Reconfiguration in Arria II
Figure
New Value
1
1
4–11, perform the following reset procedure when using the
2
3
Devices.
4
AN 558: Implementing Dynamic
Figure 4–11
“PCIe Reset Sequence” on page 4–15
Arria II Device Handbook Volume 2: Transceivers
when you are using the
4–17
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