EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 145
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–34. VCO Switchover Operating Frequency for Arria II Devices
December 2010 Altera Corporation
PLL Reconfiguration
DF vco
■
■
■
■
■
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Arria II PLLs, you can reconfigure both the counter
settings and phase-shift the PLL output clock in real time. You can also change the
charge pump and loop filter components, which dynamically affect the PLL
bandwidth. You can use these PLL components to update the output-clock frequency
and the PLL bandwidth and to phase shift in real time, without reconfiguring the
entire Arria II device.
The ability to reconfigure the PLL in real time is useful in applications that operate at
multiple frequencies. It is also useful in prototyping environments, allowing you to
sweep PLL output frequencies and adjust the output-clock phase dynamically. For
instance, a system generating test patterns is required to generate and transmit
patterns at 75 or 150 MHz, depending on the requirements of the device under test.
After a switchover event occurs, there may be a finite resynchronization period for
the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
relock depends on the PLL configuration.
If the phase relationship between the input clock to the PLL and the output clock
from the PLL is important in your design, assert areset for at least 10 ns after
performing a clock switchover.
To prevent clock glitches from propagating through your design during PLL
resynchronization or after areset is applied, use the clock enable feature of the
clock control block to disable the clock network. Wait for the locked signal to assert
and become stable before re-enabling the output clocks from the PLL at the clock
control block.
Figure 5–34
clock is lost and then increases as the VCO locks on to the backup clock.
Disable the system during clock switchover if it is not tolerant of frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO
maintains its most recent frequency. You can also use the state machine to switch
over to the secondary clock. When the PFD is re-enabled, output clock-enable
signals (clkena) can disable the clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clocks.
Primary Clock Stops Running
shows how the VCO frequency gradually decreases when the current
Switchover Occurs
Arria II Device Handbook Volume 1: Device Interfaces and Integration
VCO Tracks Secondary Clock
5–41
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