EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 663
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
December 2010 Altera Corporation
f
f
t
t
t
f
f
t
t
f
t
t
f
t
t
OUT
OUT_EXT
OUTDUTY
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
OUTCCJ_IO
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
CL B W
PLL_PSERR
ARESET
Symbol
Output frequency for internal global or regional clock
(–4 Speed Grade)
Output frequency for internal global or regional clock
(–5 Speed Grade)
Output frequency for internal global or regional clock
(–6 Speed Grade)
Output frequency for external clock output (–4 Speed Grade)
Output frequency for external clock output (–5 Speed Grade)
Output frequency for external clock output (–6 Speed Grade)
Duty cycle for external clock output (when set to 50%)
Dedicated clock output period jitter (f
Dedicated clock output period jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Time required to reconfigure PLL scan chains
Time required to reconfigure phase shift
SCANCLK frequency
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on areset signal
Description
OUT
OUT
OUT
OUT
100 MHz)
100 MHz)
100 MHz)
100 MHz)
OUT
OUT
OUT
OUT
100 MHz)
100 MHz)
100 MHz)
100 MHz)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
Typ
3.5
0.3
1.5
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
670
622
500
Max
500
500
400
300
300
650
650
100
±50
55
30
30
65
65
—
—
—
—
—
—
1
1
(5)
(5)
(5)
mUI (p–p)
mUI (p–p)
mUI (p–p)
mUI (p–p)
SCANCLK
SCANCLK
ps (p–p)
ps (p–p)
ps (p–p)
ps (p–p)
cycles
cycles
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ms
ps
ns
%
1–59
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