EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 525
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–20. FPGA Fabric-Transmitter Interface Clocking in an ×4 Bonded Channel Configuration
December 2010 Altera Corporation
Channel 3
Channel 2
Channel 1
Channel 0
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Block
CMU0 Block
Transmitter Channel PCS
Transmitter Channel PCS
Parallel PCS Clock
Parallel PCS Clock
Parallel PCS Clock
Parallel PCS Clock
Figure 2–20
channel configuration.
Divider
CMU0
Clock
/2
/2
/2
/2
shows FPGA fabric-transmitter interface clocking in an ×4 bonded
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
TX Phase
TX Phase
TX Phase
TX Phase
Input Reference Clock
FIFO
FIFO
FIFO
FIFO
/2
wrclk
wrclk
wrclk
wrclk
coreclkout
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
and Control
and Control
and Control
and Control
Channel 3
Channel 2
Channel 1
Channel 0
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
2–35
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