EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 459

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Table 1–20. SDI Mode Data Rates, refclk Frequencies, and Interface Widths in Arria II Devices (Part 2 of 2)
Figure 1–70. SDI Mode Datapath
Notes to
(1) For the frequency, data rate, and interface width supported, refer to
(2) This allows the fabric-to-transceiver interface to run below the maximum interface frequency. For more information, refer to
(3) The word aligner uses bit-slip mode. However, this block is not useful because word alignment and framing occurs after de-scrambling. Altera
December 2010 Altera Corporation
Configuration Data Rate (Mbps)
Fabric
FPGA
page
recommends driving the ALTGXB megafunction rx_bitslip signal low to prevent the word aligner from inserting bits in the received data stream.
3G
Figure
1–72.
1–70:
10-Bit or 20-Bit Interface
Figure 1–70
In HD-SDI mode, the transmitter is purely a parallel-to-serial converter. SDI
transmitter functions, such as scrambling and cyclical redundancy check (CRC) code
generation, must be implemented in the FPGA logic array. Similarly, SDI receiver
functions, such as de-scrambling, framing, and CRC checker, must be implemented in
the FPGA logic array.
2967
2970
rx_clkout
(Note 1)
tx_clkout[0]
Compensation
wrclk
shows the transceiver datapath when configured in SDI mode.
TX Phase
Frequencies (MHz)
FIFO
Support refclk
rdclk
148.35
296.7
148.5
297
/2
wrclk
Byte Serializer
(2)
/2
Receiver Channel PCS
Table 1–20 on page
Transmitter Channel PCS
rdclk
FPGA Fabric-to-Transceiver
Width
20-bit
1–72.
8B/10B Encoder
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
Parallel Recovery Clock
Byte Serializer/Deserializer
Interface
Usage
10-Bit
Used
Table 1–20 on
Transmitter Channel
Receiver Channel
Local Clock
Divider
PMA
PMA
1–73