EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 179
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Arria II Devices
OCT Support
December 2010 Altera Corporation
Table 6–11
Table 6–11. R
Left-Shift R
Arria II GZ devices support left-shift series termination control. You can use left-shift
series termination control to get the calibrated R
value of the external reference resistors connected to the RUP and RDN pins. This feature
is useful in applications that require both 25-Ω and 50-Ω calibrated R
same V
R
calibration block with 50-Ω external reference resistors.
3.3-V LVTTL/LVCMOS (2),
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
Notes to
(1) For Arria II GX devices, only the right row I/Os are available.
(2) The 3.3-V LVTTL/LVCMOS standard is supported using V
(3) Applicable for Arria II GZ devices only.
(4) Applicable for Arria II GX devices only.
S
OCT for SSTL-2 Class I and Class II I/O standards, you only need one OCT
CCIO
Table
I/O Standard
lists the I/O standards that support R
. For example, if your application requires 25-Ω and 50-Ω calibrated
S
6–11:
S
OCT Selectable I/O Standards With and Without Calibration for Arria II Devices
OCT Control for Arria II GZ Devices
(3)
(3)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Row I/O (Ω)
25
25
25
25
50
25
50
25
50
25
50
25
50
50
50
25
50
25
50
—
50
25
50
50
(4)
(4)
(4)
(4)
R
CCIO
S
OCT Termination Setting
(1)
at 3.0 V.
S
S
OCT with half of the impedance
OCT with and without calibration.
Column I/O (Ω)
S
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
OCT at the
6–21
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