EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 593

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Arria II Devices
Power Down
Power Down
Figure 4–13. Sample Reset Sequence of Four Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode with Optional gxb_powerdown Signal
December 2010 Altera Corporation
Reset/Power Down Signals
Output Status Signals
gxb_powerdown
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
pll_locked
busy
5. After assertion of the channel_reconfig_done signal, de-assert tx_digitalreset
6. Finally, wait for the rx_freqlocked signal to go high. After rx_freqlocked goes
The Quartus II software automatically selects the power down channel feature, which
takes effect when you configure the Arria II GX or GZ device. All unused transceiver
channels and blocks are powered down to reduce overall power consumption.
The gxb_powerdown signal is an optional transceiver block signal. It powers down all
the blocks in the transceiver block. The minimum pulse width for this signal is 1 s.
After power up, if you use the gxb_powerdown signal, wait for de-assertion of the busy
signal, then assert the gxb_powerdown signal for a minimum of 1 s. To finish, follow
the sequence shown in
(marker 5) and wait for at least five parallel clock cycles to de-assert the
rx_analogreset signal (marker 6).
high (marker 7), wait for 4 s to de-assert the rx_digitalreset signal (marker 8).
At this point, the receiver is ready for data traffic.
Figure
2
1
4–13.
1 μs
3
4
5
6
Arria II Device Handbook Volume 2: Transceivers
7
4 μs
8
4–19