EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 51

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Arria II Devices
Memory Features
Figure 3–2. Byte Enable Functional Waveform for MLABs
December 2010 Altera Corporation
current data: q (asynch)
contents at a1
contents at a0
contents at a2
Packed Mode Support
Address Clock Enable Support
address
byteena
inclock
wren
data
Figure 3–2
MLABs. Falling clock edges triggers the write operation in MLABs.
Arria II M9K and M144K blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements the packed mode where appropriate by placing
the physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
Arria II memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When you
configure the memory blocks in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signal is low
(disabled).
XXXX
XX
an
doutn
FFFF
shows how the wren and byteena signals control the operations of the
FFFF
FFFF
10
a0
FFFF
ABFF
FFFF
ABCD
01
a1
FFCD
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FFFF
11
a2
ABCD
ABFF
a0
ABFF
FFCD
ABCD
a1
XXXX
XX
FFCD
a2
FFCD
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